1. Field of the Invention
The present invention generally relates to data processing systems, and more particularly to a method of operating or testing a microprocessor or other computer system component using a scan chain which sequentially shifts through a serial data stream supplied by an external source.
2. Description of the Related Art
Integrated circuits are used for a wide variety of electronic applications, from simple devices such as wristwatches, to the most powerful computer systems. A microelectronic integrated circuit chip can generally be thought of as a collection of logic cells with electrical interconnections between the cells, formed on a semiconductor substrate (e.g., silicon). An integrated circuit may include a very large number of cells and require complicated connections between the cells, including different layers of conducting media available for routing.
Integrated circuits have become increasingly complex, particularly devices used as computer system components such as microprocessors, adapter chips, etc. These intricate designs are buried in the microchip layers, and so can be difficult to test or otherwise assure proper performance. Different approaches have been devised for testing integrated circuits, one of which involves the use of a serial data stream forming a test pattern which is fed into selected inputs of the integrated circuit. An early version of this technique known as Level Sensitive Scan Design (LSSD) utilized a scan line or chain which interconnects a multitude of control latches embedded in the integrated circuit. The data stream sets the control latches to predefined states as desired by the testing routine. This design has evolved into the Institute of Electrical and Electronics Engineers' Joint Test Action Group (JTAG) standard 1149 for boundary scan testing. FIG. 1 illustrates a simplified example of pervasive logic which can be embedded within a processing unit 10 to implement the JTAG standard. Processing unit 10 is constructed as a single integrated circuit semiconductor device, and is generally comprised of two processor cores 12a and 12b, a memory subsystem 14, and a JTAG interface 16. Although two processor cores are shown as included on one integrated chip 10, there could be fewer or more. Each processor core 12a, 12b has its own control logic 18a, 18b, separate sets of execution units 20a, 20b and registers/buffers 22a, 22b, respective first level (L1) caches 24a, 24b, and load/store units (LSUs) 26a, 26b. Execution units 20a, 20b include various arithmetic units such as fixed-point units and floating-point units, as well as instruction fetch units and instruction sequencer units. Registers 20a, 20b include general-purpose registers, special-purpose registers, and rename buffers. L1 caches 26a, 26b (which are preferably comprised of separate instruction and data caches in each core) and load/store units 24a, 24b communicate with memory subsystem 14 to read/write data from/to the memory hierarchy. Memory subsystem 14 may include a second level (L2) cache and a memory controller.
JTAG interface 16 has several external inputs including a data stream TDI, a state signal TMS, and a clock signal TCK, and has one external output, data stream TDO. The TCK signal is separate from the functional clocks used by cores 12a, 12b and memory subsystem 14 or other components of microprocessor 10. The JTAG inputs and output may be connected to a service processor or console device which controls a JTAG test routine. Internal to processing unit 10, JTAG 16 has a single scan chain 28 which interconnects several sets of latches or satellites that are embedded in the functional units in a ring fashion; in this example, there are sets of scan latches shown in each control logic 18a, 18b of cores 12a, 12b, and another set shown in memory subsystem 14. Operation of the test interface is governed by test access port circuitry which is essentially a state machine whose transitions are controlled by the TMS and TCK signals. While only three scan satellites are illustrated for simplicity, those skilled in the art understand that there can be hundreds of thousands of satellites in state-of-the-art designs.
Extensions to the JTAG standard 1149 can allow a system to additionally execute and control internal functional aspects of the integrated circuit. For example, the scan satellites may have internal control and error registers (along with mode, status, etc., registers) which can be used to enable and check various functions in the components. Any subset of the registers in any component on the chip may be so enabled. The chip designer can select whatever configuration might be desirable for the particular application, e.g., fault indicators for a diagnostics routine. In this manner, a service processor or test device can access any chip in a multi-processing system via JTAG interface 16 and access registers while the system is running, without interruption, to set modes, pulse controls, initiate interface alignment procedures, read status of FIRs, etc. These functions may be carried out using an additional controller (not shown) which sets an internal command register and an internal data register, and assembly code running on a component, particularly in the processor cores 12a, 12b, can allow the cores to utilize these features. For example, a core can read status bits of another component and control the logic anywhere on its own chip, and can further access components on other chips via other JTAG interfaces.